The present invention relates to a memory device having a plurality of memory cells in which, prior to the read out of the data stored in a specific memory cell among the plurality of cells, a bit line coupled to the specific memory cell is charged as to attain a given power source potential.
With the recent increase in the high integration density of the semiconductor memory device, the so-called "soft error" has become problematic in the dynamic random access memory (dynamic RAM). A trace of radioactive substances, e.g., uranium and thorium, irradiates .alpha.-rays within the package containing the semiconductor memory chips. By the irradiating .alpha.-rays, electron-hole pairs are generated. Electrons of the electron-hole pairs flow into memory nodes for data storage within the memory cells. Therefore, the data held as positive charges in the node are adversely influenced, resulting in an erroneous data read out. This phenomenon is known as the "soft error".
In a static random access memory (static RAM), a flip-flop is used for the memory cell. Since flip-flops are always connected to a power source, they are supplied with a constant current. The static RAM, unlike the dynamic RAM, has been considered free of the soft error problem. Recently, however, in the static RAM, there has also been observed the soft error as in the case of the dynamic RAM. The reason for this is that the increased integration density in the memory device causes the value of the parasitic capacitance at the data storing node to be diminished.
FIG. 1 is a block diagram showing the circuit arrangement of a conventional static RAM. The static RAM is composed of an address buffer 2 with a plurality of address input terminals 1a-1i supplied with an address signal, a timing pulse generating circuit 3, a row decoder 4, a column decoder 5, a precharge circuit 6, a plurality of bit line pairs 7a, 7a-7j, 7j, a plurality of memory cells 8, a plurality of word lines 9a-9k, a plurality of sense amplifiers 10a-10j and an input/output buffer 11. The static RAM is further provided with an input terminal for a chip enable signal and a control circuit for activating the RAM, although these components are not illustrated.
Turning to FIG. 2, a circuit diagram is illustrated as an example of a memory cell used in the static RAM of FIG. 1. This memory cell is made up of a flip-flop 20 including a couple of CMOS inverters 21, 24 which are cross-coupled with each other at the input and output terminals, as shown. The CMOS inverter 21 is composed of an N-channel MOSFET 22 and a P-channel MOSFET 23, and operates by a positive power source voltage Vcc. The CMOS inverter 24 is composed of an N-channel MOSFET 25 and a P-channel MOSFET 26, and operates by the same voltage Vcc. The memory cell is provided with a couple of transfer gates 29 and 30 as N-channel MOSFETs. The source electrodes of the transfer gates 29 and 30 are respectively coupled with a pair of data storing nodes 27 and 28 in the flip-flop 20. The drain electrodes of the transfer gates 29 and 30 are respectively connected to the bit lines 7 and 7, and the gate electrodes thereof are connected to a single word line 9. The data write and data read operations, both to and from the memory cells, are controlled by a signal on the word line 9.
FIG. 3 is a circuit diagram of one of the memory cells used in the static RAM of FIG. 1, which features a geometrical reduction of the cell area. In the memory cell, a flip-flop 20 is composed of an inverter 31, including a drive N-channel MOSFET 32 and a load resistor 33, and another inverter 34 including a drive N-channel MOSFET 35 and a load resistor 36. These inverters 31, 34 are cross-coupled with each other at the input and output terminals, as shown.
It is to be noted here that, in the FIG. 3 memory cell, P-channel MOSFETs 23 and 26 (FIG. 2) are replaced by load resistors 33 and 36, respectively. In integrated circuits having a number of circuit elements integrated therein, the element area of a resistor is much smaller than that of a MOSFET. Therefore, a memory device constructed using the FIG. 3 memory cell has a higher integration density than the memory device constructed using the FIG. 2 memory cell. Further, the resistance of the load resistors 33 and 36 are set at values larger than those of the MOSFETs 23 and 26 in an ON state, in order to reduce the power consumption in an overall circuit. For example, the resistance of the load resistors 33 and 36 are several giga ohms when the on-resistance of the MOSFETs 23 and 26 are set at several kilo ohms. For this reason, the number of charges supplied from the power source to the parasitic capacitance of the pair of data storing nodes 27, 28 in the FIG. 3 memory cell is decreased.
FIG. 4 is a circuit diagram of an example of a data latch type sense amplifier 10 used in the static RAM of FIG. 1. This sense amplifier has a flip-flop 40 including N-channel MOSFETs 41 and 42 and P-channel MOSFETs 43 and 44. Data storing nodes 45 and 46 are respectively connected to bit lines 7 and 7. A current path of an N-channel MOSFET 47 is provided between the flip-flop 40 and ground. The gate electrode of the MOSFET 47 is applied with a data sense control pulse signal .phi..sub.L generated by the timing pulse generating circuit 3.
The operation of the static RAM of FIG. 1 may now be described, with reference to the timing charts of FIG. 5. In the explanation to follow, a positive logic in which a high level is Vcc and a low level is a ground level, will be employed for the circuit. The static RAM is of the asynchronous type. A typical read out operation may be described as follows, for the sake of simplicity.
1. A chip enable signal CE has its logical state changed from low to high. Then, the static RAM is activated. The operation mode of the static RAM changes from a stand-by mode to an active mode. PA0 2. A new address AD is input to the static RAM. PA0 3. The logical state of the pulse signal .phi..sub.L is changd from high to low. The data sensing operations of the sense amplifiers 10a-10j are stopped. PA0 4. The pulse signal .phi..sub.P is changed in its logical state from low to high. The static RAM is in a precharge mode. Then, the precharge circuit 6 starts the precharge operation of bit lines 7 and 7. In the precharge operation of bit lines 7 and 7, the bit line at a low level is precharged, so that both bit lines 7 and 7 are at a high level. PA0 5. The pulse signal .phi..sub.P has its logical level changed from high to low. Then, the precharging operation of the precharge circuit 6 stops. PA0 6. The signal WL on a single word line has its logical level changed from low to high, in response to the address AD. Then, the high level pulse signal .phi..sub.L enables the pair of transfer gates 29, 30 in the plurality of memory cells 8 connected to the specific word line. For example, a signal WL on one word line 9A is at a high level. One of the data storing nodes 27 in the memory cell 8 coupled to a pair of bit lines (7a and 7a) is at a high level, while the other data storing node is at a low level. In such a case, the potential BL on one bit line 7a is kept at a high level, while the potential of the signal BL on the other bit line 7a begins to drop toward a low level. PA0 7. The logical state of the pulse signal .phi..sub.L is changed from a low level to a high level. The sense amplifiers 10a-10j begin to operate. The amplifiers 10a-10j, when operated, accelerate the potential dropping rate of the signal (BL in FIG. 5) on the bit line at a low level (of bit lines 7 and 7), and the signal quickly drops its potential to a low level. PA0 Following this, the data in the memory cell, as given by the address AD, is output through the column decoder 5 and the I/O buffer 11. At this point, the data read out operation is completed. PA0 8. Subsequently, a data write operation is executed, if necessary. Finally, the logical state of the chip enable signal CE is set, going from a high level to a low level. The signal WL on the word line 9 is set at a low level, and the static RAM is in a stand-by mode.
In the static RAM of FIG. 1, transfer gates 29 and 30, which are in the memory cell, are respectively at the same potentials on bit lines 7 and 7, which bit lines 7, 7 are connected to the drains. With this connection, a wide depletion layer is formed around the drain of the transfer gate connected to the bit line, which has been set at a high level. Due to the presence of this depletion layer, the drain of the transfer gate (not the data storing node) absorbs the electrons generated by the emitted .alpha.-rays. The depletion layer formed around the drain of the bit line having been set at a low level is narrow.
FIG. 6 shows a cross section of the structure of the transfer gate 30 in the memory cell of FIG. 3. In FIG. 6, 50 designates a P type silicon substrate, 51 an N.sup.+ type source, 52 an N.sup.+ type drain, 53 a gate oxide film, and 54 a gate electrode. If the drain 52 of the transfer gate is set in a low level, the width of the depletion layer 55 formed around the drain 52 is narrow. When the source 51 of the transfer gate 30 connected to the data storing node 28 is set in a low level, no problem arises. However, when the source 51 is set in a high level (Vcc potential) through the load resistor 36, a problem arises. Specifically, when the source 51 is set at a high level, a wide depletion layer 56 is formed around the source 51. When electrons are generated in the vicinity of the source 51 by the .alpha.-rays applied, the electrons are accelerated in the depletion layer 56 and reach the source 51. Therefore, most of the electrons are absorbed by the source 51. The absorbed electrons neutralize the positive electrons previously stored in the parasitic capacitor C, being parasitic on the data storing node 28 connected to the source 51. This results in the soft error in question. Particularly, in the static RAM employing flip-flops using the load resistors shown in FIG. 3 for the memory cell, the resistance of the load resistors connected between the pair of data storing nodes 27, 28 and the power source is very high. For this reason, when the electrons are absorbed into both nodes 27 and 28, the transfer of the positive charges from the power source is impeded and, as a result, the soft error tends to occur. As described above, in the conventional static RAM, the soft error tends to occur in the stand-by period.
While the asynchronous static RAM has been described above, the problems associated therewith also apply to the synchronous type static RAM as well.